The present invention relates to interconnect structures for high-speed microprocessors, application specific integrated circuits (ASICs), and other high-speed integrated circuits (ICs). Specifically, the present invention provides low dielectric constant (i.e., low-k) interconnect structures having enhanced circuit speed. Moreover, the structures of the present invention are mechanically stronger than conventional structures with a similar dielectric constant. The structures of the present invention comprise at least a porous, low-k dielectric film which is mechanically stronger than prior art films with a similar dielectric constant.
The semiconductor industries drive to continually improve density and performance has forced the use of advanced interconnect structures. For example, copper, Cu, has been recently introduced as a wiring technology for 0.25 xcexcm generation and below products, and by the 0.13 xcexcm generation, it is expected that the low-k dielectrics (materials having a relative dielectric constant, k, of about 3.8 or below) will be combined with such interconnects to further improve performance.
In the case of metallization, the choice of the new wiring material is reasonably straight forward, but the choice of the intermetal dielectric (IMD) is not as clear. Many new low-k dielectrics which are based on organic or glass materials have become recently available to the semiconductor industry; See, for example, co-assigned U.S. application Ser. No. 09/360,738; U.S. Pat. No. 6,440,560 to Gates, et al.; U.S. Pat. No. 5,393,712 to Rostoker, et al; U.S. Pat. No. 5,470,801 to Kapoor, et al.; and U.S. Pat. No. 5,598,026 to Kapoor, et al.
Extensive characterization and integration efforts are however needed to select appropriate candidates and then incorporate these materials into semiconductor products.
During the material selection process for IMD, emphasis is often placed on the electrical and chemical properties of the material. For example, an IMD for advanced interconnect applications must exhibit a low-dielectric constant, low-leakage, high-breakdown strength and good thermal stability at typical processing temperatures.
Although there maybe great emphasis on these properties during the initial evaluation process, mechanical properties and manufacturability issues play a large role, perhaps even a dominant role, in the selection of a dielectric for use in semiconductor manufacturing. For example, process operations such as chemical-mechanical polishing (CMP) and packaging operations may damage soft dielectric structures; therefore, the mechanical properties and manufacturability must also be taken into careful consideration when selecting an IMD.
In view of the drawbacks mentioned hereinabove concerning low-k dielectrics, there is a need for developing a new porous, low-k dielectric film that has improved mechanical properties compared with prior art low-k dielectrics.
One object of the present invention is to provide a low-k dielectric film having a dielectric constant, k, of less than about 2.0, preferably about 1.8 or less. It is noted that all dielectric constants reported herein are given in respect to a vacuum, unless otherwise stated.
Another object of the present invention is to provide a low-k dielectric film having superior mechanical properties (especially, a hardness of about 0.2 GPa or greater, and a Modulus of about 2.0 GPa or greater).
A further object of the present invention is to provide a low-k dielectric film having pores that are substantially uniform in size (size selected with a controllable diameter in the range of from about 1 to about 10 nm), and that are substantially uniformly spaced apart and essentially periodic in location.
An even further object of the present invention is to provide a low-k dielectric film that has pores having a diameter of about 1 to about 10 nm which are not connected and are separated by a low-dielectric constant matrix material.
Other objects of the present invention include:
providing a method of fabricating films which have the properties mentioned above.
providing a gapfill thin film wiring structure on an integrated circuit (IC) wherein the inventive porous, low-k dielectric film is employed as the dielectric layer between metal lines.
providing a dual damascene type thin film wiring structure on an integrated circuit (IC) wherein the inventive porous, low-k film is employed as the dielectric layer between metal wiring features.
These and other objects and advantages are achieved in the present invention by providing a porous dielectric film that comprises two phases. The first phase of the inventive dielectric film is comprised of nanometer scale pores (i.e., voids) that are substantially uniform in size, size selected with a diameter in the 1-10 nm range and that are uniformly spaced apart and essentially periodic in location. The second phase of the inventive film, which is a solid phase, is comprised of a low-dielectric constant matrix with nanometer scale particles dispersed within the matrix. The nanometer scale particles may be comprised of Si, C, O and H or another material and are substantially uniformly spaced apart and essentially periodic in location.
Specifically, the inventive porous, low-k dielectric film of the present invention comprises:
a first phase of monodispersed pores having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially located on sites of a three-dimensional periodic lattice; and
a second phase surrounding said first phase, wherein said second phase is a solid phase which includes (i) an ordered element that is composed of nanoparticles having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially arranged on sites of a three-dimensional periodic lattice, and (ii) a disordered element comprised of a dielectric material having a dielectric constant of less than about 2.8.
The nanoparticles employed in the present invention may be comprised of Si, C, O and H or any other nanoparticle that fits the above description.
A further aspect of the present invention relates to interconnect structures which include at least the porous, low-k dielectric film of the present invention as one of the essential structural components. In the interconnect structures, the inventive porous, low-k dielectric is employed as the dielectric layer that is formed between metal wiring features.
Another aspect of the present invention relates to a method of fabricating the above-mentioned porous, low-k dielectric film. Specifically, the method of the present invention comprises the steps of:
(a) coating a suspension of water soluble or water vapor soluble oxide particles with a surface ligand group which is effective in preventing agglomeration of said oxide particles, yet maintains solubility of the oxide particles in said suspension, while separately forming monodispersed, e.g. SiCOH, particles having a particle diameter of from about 1 to about 10 mn;
(b) adding said coated water soluble or water vapor soluble oxide particles and said monodispersed particles to a solution containing a dielectric binder material having a dielectric constant of about 2.8 or less so as to form a precursor mixture;
(c) coating said precursor mixture on a surface of a substrate;
(d) subjecting said coated precursor mixture to a curing process, said curing process including at least a step which is capable of ordering of said particles in a three-dimensional lattice and a step of forming a crosslinked film;
(e) removing said coated water soluble or water vapor soluble oxide particles from said crosslinked film so as to form pores in said film; and
(f) annealing said film containing said pores so as to remove residual water and hydroxyl groups from said film, wherein said film comprises a first phase of monodispersed pores having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially located on sites of a three-dimensional periodic lattice originally occupied by the water soluble or vapor soluble oxide particles; and a second phase surrounding said first phase, wherein said second phase is a solid phase which includes (i) an ordered element that is composed of nanoparticles having a diameter of from about 1 to about 10 nm that are substantially uniformly spaced apart and are essentially arranged on sites of a three-dimensional periodic lattice, and (ii) a disordered element comprised of said binder.